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| author | Nebuleon <nebuleon@alakazam> | 2017-05-21 19:32:34 +0000 |
|---|---|---|
| committer | Nebuleon <nebuleon@alakazam> | 2017-05-21 19:32:34 +0000 |
| commit | 97cd994ae7806a3d34c26fa15c791fed1935e7ff (patch) | |
| tree | 099cc0ccf5df501d2d353165b0410d840796136d | |
| parent | 0c69127421049e25aa8ea693fc8f8d09966bdbca (diff) | |
| download | ReGBA-97cd994ae7806a3d34c26fa15c791fed1935e7ff.zip ReGBA-97cd994ae7806a3d34c26fa15c791fed1935e7ff.tar.gz ReGBA-97cd994ae7806a3d34c26fa15c791fed1935e7ff.tar.bz2 | |
dstwo: Rework ReGBA_MakeCodeVisible for efficiency
| -rw-r--r-- | source/dstwo/port-asm.S | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/source/dstwo/port-asm.S b/source/dstwo/port-asm.S index a4359af..a2208c7 100644 --- a/source/dstwo/port-asm.S +++ b/source/dstwo/port-asm.S @@ -1,6 +1,7 @@ .global ReGBA_MakeCodeVisible .set noat +.set noreorder .ent ReGBA_MakeCodeVisible @@ -28,13 +29,15 @@ ReGBA_MakeCodeVisible: # Now git 'er done. 1: cache 0x19, ($4) # Data Writeback (needs to be 0x15, WB/Invalidate, - sync # on general MIPS processors) + # on general MIPS processors) cache 0x10, ($4) # Instruction Invalidate addiu $4, $4, 32 # go to the next cache line sltu $1, $4, $5 # if Code < End bne $1, $0, 1b # goto 1 nop # cannot delay usefully here + sync # guard against memory hazards + 2: jr $ra # return to caller nop # cannot delay usefully here |